CPU Interrupts Simulator
On accept, CPU
pushes current register contents
to the stack; on return, CPU
pops and reloads
them. Higher-priority interrupts can nest (LIFO stack).
Registers • PUSH/POP • Priority • Fixed message area
Controls
Cycle
0000
Speed
6
Auto Run
Pause
Step
Reset
Interrupts enabled (I flag)
Allow nested interrupts
CPU
USER
Running user code
PC
0x1000
Part of saved context
Queue
0
Pending interrupts
Stack depth
0
Saved register sets
I flag
ON
Maskable interrupts
Current priority
—
Lower number = higher
Reset clears queue/stack and turns off all Auto sources to avoid confusion.
Interrupt sources
Trigger or Auto-generate
Emergency (NMI)
Non-maskable, highest priority
prio 0
ISR length
3 cycles
5 cycles
8 cycles
Trigger
Auto
Disk I/O complete
Important device completion
prio 1
ISR length
4 cycles
6 cycles
9 cycles
Trigger
Auto
System timer
Regular tick / time slice
prio 2
ISR length
2 cycles
4 cycles
7 cycles
Trigger
Auto
Keyboard
User input
prio 3
ISR length
2 cycles
4 cycles
6 cycles
Trigger
Auto
Event log
Per cycle
Simulation
Priority + Stack + Registers
CPU now
—
USER
User program
Executing next instruction
PC:
0x1000
CPU registers (live)
These values are what get PUSHed/POPed
PC
0x1000
ACC
0x00
R0
0x12
R1
0x34
R2
0x56
R3
0x78
FLAGS
I=ON
SP (depth)
0
In this model, the CPU checks interrupts between instructions. When accepted, the current register values are saved on the stack.
Pending interrupt queue
Highest priority accepted when allowed
Queue empty. Trigger an interrupt source on the right.
Stack (saved CPU registers)
PUSH on accept • POP on return • LIFO