CPU Interrupts Simulator

Simulation controls

Speed 6

Interrupts enabled
I flag for maskable interrupts

Allow nested interrupts
higher priority may pre-empt

CPU

USER

Running user code

0x1000

Saved in context

Queue

Pending requests

Stack

Saved contexts

I flag

Maskable enable

Priority

—

Lower = higher

Interrupt sources · priority model

Emergency (NMI)

Non-maskable example · ISR 0x9000

prio 0

ISR

Disk I/O complete

Device completion · ISR 0x9100

prio 1

ISR

System timer

Regular timer event · ISR 0x9200

prio 2

ISR

Keyboard

User input · ISR 0x9300

prio 3

ISR

CPU · Interrupt Handling One step = one simplified FDE cycle followed by the interrupt check · watch PC branch to an ISR and return

LIVE MODEL

CPU now

—

USER

User program

Executing next instruction

PC: 0x1000

CPU registers · live

PC, ACC, MAR, MDR, CIR and FLAGS are shown in the saved context

0x1000

ACC

0x00

MAR

0x1000

MDR

0x0000

CIR

0x0000

FLAGS

I=ON

SP · depth

Pending interrupt queue

highest eligible priority first

Queue empty. Trigger an interrupt source on the left.

Memory stack · saved CPU register context

What is happening

Running the user program

The CPU is executing normal instructions and checking for eligible interrupts between instructions.

I=ON: maskable interrupts may be accepted. NMI is also eligible.

Core interrupt sequence

1Complete FDE: the current instruction finishes before the interrupt check.

2Check interrupts: the CPU considers pending requests, priority and interrupt-enable state.

3Save context: the register snapshot is PUSHed onto the memory stack.

4Branch to ISR: the PC is loaded with the relevant ISR address.

5Run ISR: the service routine executes. A higher-priority eligible interrupt can create another stack frame.

6Restore context: the saved registers are POPed from the stack.

7Resume: the restored PC continues the interrupted FDE sequence.

Event log

Model scope

Teaching model: the core interrupt sequence is shown explicitly. Priority numbers, the particular NMI example, interrupt-enable flag behaviour, ISR addresses and exactly which registers are automatically saved are processor-specific. This simulator uses priority 0 as the highest priority and illustrative ISR addresses so the mechanism is visible.