Advanced CPU Simulator — OCR A Level H446

A-level focus

OCR H446 · 1.1.1

Processor components, buses, register effects during FDE, pipelining, CPU performance factors and processor architectures.

Teaching program

Playback

Animation speedNormal

Processor key

Control Unit — coordination / decode

ALU — arithmetic, logic, shifts

Dedicated registers

Address bus — address from CPU

Data bus — bidirectional

Control bus — control signals

Teaching ISA: the assembly mnemonics are deliberately simple. OCR requires students to relate processor components to assembly, but does not prescribe this exact instruction set or binary encoding.

Binary teaching processor

Words, opcodes & operands

Follow an OCR-style 8-bit instruction word from RAM into the CIR, then watch a dedicated Decode Unit interpret its 4-bit opcode and 4-bit operand.

Playback

Animation speedNormal

Teaching model

8-bit instruction word

4-bit address bus → 16 locations

8-bit data bus → one word per transfer

Decode Unit interprets opcode + operand

Word: a fixed-size group of bits treated as one unit. In this teaching processor a word is 8 bits. The widths are deliberately small for teaching and are not universal CPU sizes.

Pipeline controls

3-stage teaching pipeline

Fetch, Decode and Execute overlap across different instructions. The model demonstrates throughput, not a claim that each instruction itself becomes faster.

Key idea

OCR wording: pipelining allows the next instruction to be fetched while earlier instructions are being decoded/executed, increasing instruction throughput and reducing idle processor components.

Architecture comparison

Three models

Select a diagram to compare memory organisation and instruction/data pathways.

Exam distinction

Do not oversimplify: real contemporary processors vary. A common arrangement is unified main memory with separate instruction and data caches close to the CPU.

Performance factors

Clock · cores · cache

Explore each OCR factor separately. The simulator avoids a fake single “performance percentage” because real performance depends on workload and architecture.

Exam caution

More is not automatically proportional. Higher clock speed, more cores and larger/faster cache can improve performance, but benefits depend on heat/power, parallelism and cache behaviour.

Processor components & Fetch–Decode–Execute

Follow register transfers, buses, control signals, opcode/operand decoding and instruction execution.

OCR H446 · 1.1.1(a–b)

Central Processing Unit (CPU)CU · ALU · dedicated registers

Processing & control coordinates, decodes, calculates

Control Unit (CU)

coordinates components · decodes CIR · issues control signals

Current CU activity

Waiting for the first micro-step.

Opcode—

Operand—

Arithmetic Logic Unit (ALU)

arithmetic · logic · shift operations

ALU activity

Idle — no ALU operation

Dedicated registers very fast storage inside the processor

Program Counter

address of next instruction

MAR

Memory Address Register

address currently being accessed

—

MDR

Memory Data Register

value moving to / from memory

—

CIR

Current Instruction Register

current instruction: opcode + operand

—

ACC

Accumulator

working value / intermediate result

Address bus

Data bus

Control bus

Main Memory (RAM)instructions + data

Address	Contents

Von Neumann model: instructions and data share main memory. Address bus selects a location; data moves on the data bus; READ/WRITE travels on the control bus.

Address bus: CPU → memory/I/OData bus: bidirectionalControl bus: control/timing signalsCurrent instruction: not yet fetched

Binary instruction words & Decode Unit

Fetch an 8-bit word from RAM, split it into opcode and operand, then watch the Decode Unit determine the instruction.

OCR-style binary teaching model

Central Processing Unit (CPU)binary datapath · decode unit · registers

Program CounterPC

4-bit address of next instruction

0000

Memory Address RegisterMAR

address currently being accessed

—

AccumulatorACC

8-bit working/result word

0000 0000

Memory Data RegisterMDR

8-bit word moving to/from RAM

—

Current Instruction RegisterCIR

current 8-bit instruction word

—

Opcode—

Operand—

Control UnitCU

coordinates transfers and control signals

READY

Arithmetic Logic UnitALU

operates on binary values

ALU activity

Idle — no ALU operation

CacheC

Included to mirror the OCR processor diagram. This mode focuses on instruction encoding and decoding rather than cache behaviour.

Decode Unit — instruction lookup

Opcode	Operand	Instruction

4-bit Address bus

8-bit Data bus

Control bus

Main Memory (RAM)16 locations · one 8-bit word each

Address	8-bit word

4-bit address bus → 2⁴ = 16 locations8-bit data bus → one 8-bit word per transferCurrent binary instruction: not yet fetched

New concept: word

One fixed-size binary unit

A word is a fixed-size group of bits treated as a unit by a processor or memory system. In this deliberately small teaching model, one memory word is 8 bits.

01010101

one 8-bit word · the space is only for readability

Address width4 bits → 16 locations

Word / data width8 bits

Precision: these widths belong to this teaching model. Real processors can have different word, data-bus and address widths.

Current decode

Waiting for an instruction

The fetched 8-bit instruction word will be copied to the CIR and split into two 4-bit fields.

Instruction word

CIR—

Opcode—

Operand—

Decoded as—

What is happening

Ready to fetch binary

PC starts at binary address 0000. Follow the word across the address, data and control buses.

Micro-operation / signalPress Next binary step

Address busidle

Data busidle

Control busidle

Output: —

Instruction pipelining

Observe Fetch, Decode and Execute overlapping across different instructions.

OCR H446 · 1.1.1(d)

Clock cycle

current pipeline cycle

Completed

instructions completed

Pipeline state

Empty

fill → steady state → drain

Ideal throughput

1 / cycle

after a 3-stage pipeline fills

Start: click Next clock. Without pipelining, one instruction would complete all three stages before the next starts. In this idealised pipeline, different instructions can occupy different stages simultaneously.

Pipeline model: 3 stages · one cycle per stageThroughput improves; individual instruction latency is not necessarily reduced.

Von Neumann, Harvard & contemporary architectures

Compare where instructions/data are stored and how their pathways are organised.

OCR H446 · 1.1.1(e)

Von Neumann

Instructions and data share the same main memory and shared pathways.

Key feature: one memory space for instructions and data. The same system-bus resources are shared by both kinds of transfer.

Harvard

Instructions and data use separate memories and separate buses.

Key feature: separate instruction/data storage and pathways can permit simultaneous access. Memory sizes/word widths can differ between the two sides.

Contemporary / modified Harvard

A common modern arrangement mixes both ideas.

Common contemporary pattern: unified main memory but separate instruction/data caches close to the CPU. This is often described as modified Harvard.

These are architectural models; real processors may combine features.Selected: Von Neumann

Factors affecting CPU performance

Explore clock speed, number of cores and cache without pretending they combine into one universal benchmark.

OCR H446 · 1.1.1(c)

Clock speed

How many clock cycles occur each second. A higher clock can allow more processor operations per second, all else equal.

Clock frequency3.0 GHz

Clock cycles per second

3.0 billion

1 GHz = 1 billion cycles/s

Limitation: higher clock speed can increase heat/power use, and different CPU designs may do different amounts of useful work per cycle.

Number of cores

Multiple cores can execute instructions independently, but software must contain work that can run in parallel.

CPU cores4 cores

Parallel workload: several cores can be useful at the same time, increasing potential throughput.

Cache

Small, fast memory close to the CPU stores recently/frequently used instructions or data to reduce slower main-memory accesses.

Cache capacity8 items

Working set

Cache fits

8/12

Illustrative hit opportunity

67%

teaching model for repeated working-set access

Important: cache performance depends on access patterns, cache hierarchy, replacement policy and latency. Capacity alone does not determine speed.

OCR factors: clock speed · number of cores · cacheEffects depend on workload and processor design.